1. Field of the Invention
The present specification relates generally to a MOS (Metal Oxide Semiconductor) transistor and a semiconductor apparatus employing a MOS transistor, and more particularly to a MOS transistor and such a semiconductor apparatus having various threshold voltages.
2. Discussion of the Related Art
It is known that a MOS transistor can be operated in a saturation range. When so operated, drain current variation due to a drain voltage variation is relatively small. This insensitivity of drain current to drain voltage is useful in a constant current source used in a differential amplifier circuit as well as in a MOS transistor section included in a current mirror circuit. These applications generally require small variations in current value corresponding to a change in a power source voltage. Such performance is also required when a MOS transistor operates as a reference current source.
In this regard, a MOS transistor should generally have a small channel length variation effect, i.e., an excellent λ performance. Such a channel length variation effect (λ) is a phenomenon in which drain current increases when a drain side depletion layer extends to a source side as a drain voltage increases. According to the channel length variation effect, an effective channel length becomes shorter during operation of the transistor in saturation. To achieve good λ performance, a MOS transistor is conventionally designed with extremely long effective channel length.
However, a MOS transistor with long effective channel length is unsuitable when for flowing a significant current. In addition, a MOS transistor used in a differential amplifier circuit is required to have a current value varying widely (i.e., a β performance) in relation to changes in gate voltage. Accordingly, a channel width of the transistor might be adjusted wider in proportion to an increase in effective channel length. As a result, a differential amplifier circuit having a high performance necessarily needs a large channel area. Thus, a designer may be required to compromise transistor performance to achieve limited channel size.
In view of such a problem, a MOS transistor excellent in both the λ and β performances, the requirements of which are conflicting to each other, has been demanded even in a small area. Further, such a MOS transistor has been demanded in an enhancement type transistor, a depletion type transistor, a Pch-MOS transistor, an Nch-MOS transistor, and the like.
When MOS transistors are designed to include various threshold voltages on the same semiconductor substrate, threshold voltages are differentiated based upon the thicknesses of gate oxide films, or densities of impurity in channel regions which in turn are determined by the amount of channel regions beneath a gate oxide film.
For example, the gate oxide film is typically formed in different thicknesses in the plurality of regions forming MOS transistors. Specifically, a silicon oxide film is formed on a surface of a semiconductor substrate. A silicon nitride film is then formed on the silicon oxide film in an element device formation region. Then, an element device separation film is formed using a LOCOS (Local Oxidation of Silicon) method. A resist film having an opening is then formed at a position corresponding to an element device formation region that forms a first gate oxide film. Silicon nitride and silicon oxide films in the openings are removed using the resist film. Then, a first gate oxide film is selectively formed by thermal oxidization. After removal of the silicon nitride and silicon oxide films within the element device formation region forming a second gate oxide film, the second gate oxide film is selectively formed to a different thickness from that of the first gate oxide film as discussed in Japanese Patent application Laid Open No. 10-178102.
An exemplary method of varying the density of impurities in channel regions by changing a channel dopant value in a plurality of element device formation regions is discussed in Japanese Patent Application Laid Open No. 08-274330. Specifically, a pair of channel regions is disposed in element device formation regions having a first impurity density and a second impurity density. The first impurity density is determined by a surface density of a P-type semiconductor substrate. The second impurity density is determined by implementation of impurity performed by ion implantation or the like into a region selected by a pattern of an impurity implementation use mask. In addition, each of the channel regions of the first and second impurity densities is divided into a plurality of planar shapes. As shown in the impurity implementation use mask used when ion is implanted and a channel region having a second impurity density is formed, a planar area ratio between channel regions of the first and second impurity densities and a channel dope value given to the channel region are changed by changing the pattern at a plurality of element device formation regions.